This application relies from priority upon Korean Patent Application No. 2000-14798, filed on Mar. 23, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention is related to semiconductor devices, and more particularly to semiconductor fuses.
For many years fuses have been used in semiconductor circuits for a variety of purposes. For example, memory circuits typically use fuses to implement memory redundancy. Word line redundancy hardware exists to replace inoperable bit cells or word lines at manufacturing test. The effect of using memory redundancy is to increase effective yield. The improvement in yield is accomplished by programming fuses or fuse circuits to remain conductive or to become electrically open depending upon what memory circuit is needed. Another common use of fuse technology in semiconductors is to implement electronic chip identification. Chip identification is accomplished by uniquely identifying the source of each chip including a lot, a wafer, and an X/Y coordinate location on a wafer so that a manufacturer can easily retrieve and report process data for a given integrated circuit.
Fuses have commonly been implemented in semiconductors with either polysilicon or metal. Metals which have been used in the past include aluminum and tungsten. Regardless of the material used to implement the fuse, programming circuitry is required in order to control whether or not the fuse has been blown and to indicate the status of the fuses conductivity. Such examples of a fuse circuit, which is programmable, are disclosed in U.S. Pat. No. 4,446,534 entitled xe2x80x9cProgrammable Fuse Circuitxe2x80x9d and in U.S. Pat. No. 5,953,279 entitled xe2x80x9cFuse Option Circuit For Memory Devicexe2x80x9d. Semiconductor fuses are typically made non-conductive either by application of a large voltage (relative to power supply voltage magnitude) or by use of laser light. In either event, a circuit is required to indicate the existing status of whether or not the fuse has successfully been made nonconductive.
A conventional fuse circuit, which is used in the art, is illustrated in FIG. 1. A fuse circuit 10 includes a first fuse resistor element 14, which is connected between a node marked with Vcc through a PMOS transistor 12 and a node marked with ND1. A second fuse resistor element 18 is connected between the node Vcc through a PMOS transistor 16 and a node marked with ND2. The PMOS transistors 12 and 16 have their gates or control electrodes connected to receive a signal PEFE in common. An NMOS transistor 20 has a drain or a first electrode connected to the node ND 1, a source or a second electrode connected to a ground voltage, and a gate connected to the node ND2. An inverter 24 has an input connected to the node ND2 and an output for providing a signal marked with xe2x80x9cFUSE OUTxe2x80x9d. An NMOS transistor 26 for programming a fuse has a drain connected to the node ND 1, a source connected to the ground voltage, and a gate connected to receive a fuse program pulse signal FCUT.
In FIG. 1, the fuse resistor element 14 is an electrically programmable fuse, and the fuse resistor element 18 acting as a resistor is configured so as to have larger resistor value than that of the fuse resistor element 14 when the fuse resistor element 14 is at an intact state (or a conductive state). On the other hand, the fuse resistor element 18 is configured so as to less resistor value than that of the fuse resistor element 14 when the fuse resistor element 14 is at a non-conductive state.
Although programmed by application of a large voltage, an electrically programmable fuse either is not cut perfectly or is again connected by various causes after being cut. Substantially, after a program operation is carried out, the electrically programmable fuse has an increased resistor value as compared with that before programming. A problem of the fuse circuit in FIG. 1 using such characteristic is that, although the resistor value of the fuse resistor element 14 is increased over that before a program operation (i.e., although it is larger than a resistor value of the fuse resistor element 18), the output signal FUSE OUT is maintained at a logic high level set before the program operation regardless of the program operation. A more detailed description is as follow.
In the fuse circuit 10 of FIG. 1, latch circuit consisting of the NMOS transistors 20 and 22 senses a resistor difference between the fuse resistor elements 14 and 18 as a voltage difference between the nodes ND1 and ND2. For example, in a case where a resistor value of the fuse resistor element 14 is less than that of the fuse resistor element 18 (that is, before the fuse resistor element 14 is programmed), the nodes ND1 and ND2 are set to a logic low level and a logic high level by a latch operation of the NMOS transistors 20 and 22 at power-up, because capacitive parasitic loading of the node ND1 is less than that of the node ND2.
Then, in the case that the resistor value of the fuse resistor element 14 is larger than that of the fuse resistor element 18 (that is, after the fuse resistor element 14 is programmed), the nodes ND1 and ND2 may be set to a logic high level and a logic low level. But, the nodes ND1 and ND2 are maintained at logic states before programming. This is because voltages of the node ND1 and ND2 are determined not by a resistor difference between the fuse resistor elements 14 and 18, but by capacitive parasitic loading of the respective nodes ND1 and ND2. Therefore, although a resistor value of the fuse resistor element 14 is varied (or increased) before and after programming, the fuse circuit 10 outputs the signal FUSE OUT of a logic low level indicating that the fuse resistor element 14 is not programmed.
As a result, the voltages of the nodes ND1 and ND2 of the fuse circuit 10, which senses a resistor difference of the elements 14 and 18, are determined (or fixed) according to capacitive parasitic loading of the respective nodes ND1 and ND2 regardless of a program operation of the fuse resistor element 14. Therefore, the fuse circuit 10 has a shortcoming indicating a conductive state of the fuse resistor element 14 at an output of the inverter 24 after the fuse resistor element 14 is substantially programmed. This causes a reliability problem.
It is therefore an object of the invention to provide a fuse circuit and a program status detecting method thereof, which are capable of improving a reliability of an electrically programmable fuse.
This and other objects, advantages and features of the present invention are provided by fuse option circuit that comprises a first fuse element having first and second terminals, wherein the first terminal of the first fuse element is connected to a first power terminal; a second fuse element having first and second terminals, wherein the first terminal of the second fuse element is connected to the first power terminal; first and second nodes connected to the second terminals of the first and second fuse elements, respectively; means for sensing a difference of currents flowing through the first and second fuse elements, wherein the sensing means determines voltages of the first and second nodes depending on the current difference thus sensed; and means for amplifying voltages of the first and second nodes either to voltages of the first and second power terminals or to voltages of the second and first power terminals, respectively.
In this embodiment, the sensing means comprises a first transistor coupled between the first node and the second power terminal; and a second transistor coupled between the second node and the second power terminal, wherein the first and second transistors are simultaneously switched on/off according to a control pulse signal.
In this embodiment, the amplifying means comprises a third transistor which has a current path formed between the first node and the second power terminal and a gate electrode coupled to the second node; and a fourth transistor which has a current path formed between the second node and the second power terminal and a gate electrode coupled to the first node, wherein the third and fourth transistors serve as a latch circuit.